1 ? fn8226.1 caution: these devices are sensitive to electrosta tic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | intersil (and design) is a registered trademark of intersil americas inc. copyright intersil americas inc. 2006. all rights reserved all other trademarks mentioned are the property of their respective owners. ISL88021, isl88022 triple voltage monitor with adjustable power-on-reset and undervoltage/ overvoltage monitoring capability the ISL88021 and isl88022 family of devices are customizable triple voltage-m onitoring supervisors that assert a reset if any of the monitored voltages becomes non-compliant. they offer popular functions such as power-on-reset timing contro l with both reset and reset outputs, supply voltage supervision, both under or overvoltage detection, and manual reset assertion. by offering these features in a small 8 ld msop package, the ISL88021 and isl88022 can lower system cost, reduce board space requirements and increase the reliability of systems. applying a voltage to v dd activates the power-on-reset circuit which holds reset low for an adjustable period of time. this allows the power s upply and system oscillator to stabilize before the processor can execute code. low v dd detection circuitry protects the user?s system from low voltage conditions, resetting the system when v dd falls below its minimum preset voltage threshold v th1 . reset remains asserted until v dd returns to its proper operating level and stabilizes. two additional voltage monitoring inputs, v2mon (preset) and v3mon (adjustable), monitor other supplies to provide reliable system operation. the ISL88021 v3mon input monitors for undervoltage (uv) conditions whereas the isl88022 v3mon input allows monitoring for overvoltage (ov) conditions. the monitored voltage on v3mon on either device is compared via a resistor divider to a 600mv internal reference. hence, any voltage more or less positive than this reference can be accurately monitored to me et specific system level requirements or to fine-tune t he threshold for applications requiring higher precision. these devices also let users increase the power-on-reset time-out delay by connecting a capacitor between c por and ground. this lengthens the period of an internal clock counter thereby increasing the time between voltage compliance and reset outputs signaling. a manual reset input provides debounce circuitry for minimum reset component count. features ? triple voltage monitor and reset assertion ?low v dd detection and reset assertion - adjustable reset threshold voltages - 0.6v 6mv over -40c to +85c - reset signal valid to v dd = 1v ? 140ms minimum reset pulse de lay that is customizable using an external capacitor ? both rst and rst outputs available ? undervoltage/overvoltage monitoring capability ? low 20a consumption ? small 8 ld msop package ? pb-free plus anneal available (rohs compliant) applications ? process control systems ? intelligent instruments ? embedded control systems ? computer systems ? portable/battery-powered equipment ? multi-voltage systems pinout ISL88021, isl88022 (8 ld msop) top view 1 2 3 4 8 7 6 5 v dd v2mon gnd rst rst c por v3mon mr data sheet september 18, 2006
2 fn8226.1 september 18, 2006 block diagrams ordering information (see notes) part number part marking v dd v trip1 v2mo v trip2 v3mon type package ISL88021iu8faz anm 3.09v 1.69v uv 8 ld msop ISL88021iu8fcz anl 3.09v 2.32v uv 8 ld msop ISL88021iu8fez 3.09v 2.92v uv 8 ld msop ISL88021iu8ffz 3.09v 3.09v uv 8 ld msop ISL88021iu8haz 4.64v 1.69v uv 8 ld msop ISL88021iu8hcz 4.64v 2.32v uv 8 ld msop ISL88021iu8hez ank 4.64v 2.92v uv 8 ld msop ISL88021iu8hfz anj 4.64v 3.09v uv 8 ld msop isl88022iu8faz anq 3.09v 1.69v ov 8 ld msop isl88022iu8fcz anp 3.09v 2.32v ov 8 ld msop isl88022iu8fez 3.09v 2.92v ov 8 ld msop isl88022iu8ffz 3.09v 3.09v ov 8 ld msop isl88022iu8haz 4.64v 1.69v ov 8 ld msop isl88022iu8hcz 4.64v 2.32v ov 8 ld msop isl88022iu8hez ano 4.64v 2.92v ov 8 ld msop isl88022iu8hfz ann 4.64v 3.09v ov 8 ld msop notes: 1. standard versions are shown in bold. for non-standard versions, please contact factor y for availability. 2. add ?-tk? suffix for tape and reel. 3. intersil pb-free plus anneal products employ special pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are rohs compliant and compatible with both snpb and pb-free soldering operations. intersil pb-free products are msl classified at pb-free peak reflow temperatures that meet or exceed the pb-free requirements of ipc/jedec j std-020. ordering information (see notes) (continued) part number part marking v dd v trip1 v2mo v trip2 v3mon type package v dd c por por mr pb rst gnd v ref v2mon v3mon isl88022 ISL88021 rst v dd c por por mr pb gnd v ref v2mon v3mon rst rst pin descriptions ISL88021 isl88022 name function 11 mr active-low open drain manual reset input 22 v dd power supply input 3 3 v2mon second undervoltage monitor input 4 4 gnd ground 5 v3mon undervoltage monitor input 5 v3mon overvoltage monitor input 66 c por set power-on-reset timeout delay 77 rst active-low open drain reset output 8 8 rst active-high push-pull reset output ISL88021, isl88022
3 fn8226.1 september 18, 2006 absolute maximum rati ngs thermal information temperature under bias . . . . . . . . . . . . . . . . . . . . -40 c to +85 c voltage on any pin with respect to gnd . . . . . . . . . . . -1.0v to +7v d.c. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5ma recommended operating conditions industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40c to +85c thermal resistance (typical, note 1) ja (c/w) msop package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 maximum junction temperature (plastic package) . . . . . . . +150c maximum storage temperature range . . . . . . . . . .-65c to +150c maximum lead temperature (soldering 10s) . . . . . . . . . . . . +300c (msop - lead tips only) caution: stresses above those listed in ?absolute maximum ratings? may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. note: 1. ja is measured with the component mounted on a high effective therma l conductivity test board in free air. see tech brief tb379 f or details. electrical specifications over the recommended operating conditi ons unless otherwise specified. symbol parameter test conditions min typ max units v dd supply voltage range 2.0 5.5 v i dd1 v dd supply current v dd = 5.0v 12.5 15 a i dd2 v2mon input current v2mon = 3.3v 5.5 6 a i dda v3mon input current v3mon = 1.0v 19 100 na voltage thresholds v th1 fixed voltage trip point for v dd ISL88021/22iu8 h xz 4.565 4.649 4.733 v ISL88021/22iu8 f xz 3.029 3.085 3.141 v v th1hyst hysteresis of v th1 v th1 = 4.64v 46 mv v th1 = 3.09v 37 mv v th2 fixed voltage trip point for v2mon ISL88021/22iu8x f z 3.034 3.090 3.146 v ISL88021/22iu8x e z 2.894 2.947 3.000 v ISL88021/22iu8x c z 2.290 2.332 2.374 v ISL88021/22iu8x a z 1.660 1.690 1.720 v v th2hyst hysteresis of v th2 v th2 = 3.09v 37 mv v th2 = 2.92v 29 mv v th2 = 2.32v 23 mv v th2 = 2.19v 22 mv v th2 = 1.69v 17 mv v th3 v3mon threshold voltage v th for v3mon on ISL88021 0.594 0.605 0.616 v v th for v3mon on isl88022 0.587 0.595 0.603 v v refhyst hysteresis voltage 3mv reset v ol reset output voltage low v dd 3.3v, sinking 2.5ma 0.05 0.40 v v dd < 3.3v, sinking 1.5ma 0.05 0.40 v v oh rst output voltage high v dd 3.3v, sourcing 2.5ma v dd -0.6 v dd -0.4 v v dd < 3.3v, sourcing 1.5ma v dd -0.6 v dd -0.4 v t rpd v th to reset asserted delay 10 s t por por timeout delay c por is open 140 200 ms c load load capacitance on reset pins 5 pf ISL88021, isl88022
4 fn8226.1 september 18, 2006 functional description the ISL88021 and isl88022 devices incorporate such features as power-on-reset control, supply voltage supervision, undervoltage or overvoltage monitoring, and manual reset assertion. the ISL88021 and isl88022 devices provide common preset threshold voltages on both v dd and v2mon and for an optional resistor divider network on v3mon to provide custom voltage monitoring of voltages greater than 0.6v. an optional capacitor can be connected between the c por pin and gnd to increase the nominal 200ms t por delay. figure 7 illustrates operational functionality with a timing diagram. voltage monitoring during normal operation, the ISL88021 and isl88022 monitor the voltage levels on v dd , v2mon and v3mon. the ISL88021 asserts reset if any one of these voltages fall below their respective voltage trip points and in the case of isl88022 above the voltage trip point on the v3mon input. the reset signal effectively prevents the microprocessor from operating during a power failure, brownout or over voltage condition. this signal remains active until all monitored voltages meet all voltage threshold requirements for the reset time delay period t por . note that both reset and reset signals are provided for design flexibility. figure 1 illustrates the vdd, v2mon and v3mon input threshold voltages for the various available options. power-on-reset (por) applying power to the ISL88021 and isl88022 devices activates a por circuit which holds the reset pin low once v dd > 1v. this signal provides several benefits: ? it prevents the system microprocessor from starting to operate with insufficient voltage. ? it prevents the processor from operating prior to stabilization of the oscillator. ? it ensures that the monitored device is held out of operation until internal registers are properly loaded. ? it allows time for an fpga to download its configuration prior to initialization of the circuit. when all of the monitored voltages meet their respective input voltage requirements for the specified reset timeout delay t por , the por circuit simultaneously pulls the rst output low and releases the rst output to a llow the system to begin operation. adjusting t por on the ISL88021 and isl88022, users can adjust the power-on-reset timeout delay (t por ) to many times the nominal t por . figure 2 illustrates the effect of capacitance on the c por pin to ground, showing changing t por with a graph normalized to 175ms for an open c por pin. the maximum recommended capacitance that should be placed on the c por pin is 50pf. note: care should be taken in pcb layout and capacitor placement in order to eliminate stray capacitance as much as possible, which contributes to t por error. manual reset v mrl mr input voltage low 0.8 v v mrh mr input voltage high v dd -0.6 v t mr mr minimum pulse width 550 ns r pu internal pull-up resistor 20 k electrical specifications over the recommended operating conditi ons unless otherwise specified. (continued) symbol parameter test conditions min typ max units figure 1. vdd, v2mon, v3mon vth vs temp 0.000 0.500 1.000 1.500 2.000 2.500 3.000 3.500 4.000 4.500 5.000 -40 25 85 temperature (c) vdd, v2mon, v3mon vth (v) vth = 4.64v vth = 1.69v vth = 3.09v vth = 2.92v vth = 2.32v vth = 0.60v figure 2. normalized t por vs c por graph 0 2 4 6 8 10 1 5 9 13 17 21 25 29 33 37 41 45 c por (pf) normalized t por ISL88021, isl88022
5 fn8226.1 september 18, 2006 manual reset the manual reset input (mr ) allows the user to trigger a reset by using a push-button switch or by signaling that pin low. the mr input is an active low debounced input. by connecting a push-button directly from mr to ground, the designer adds manual system reset capability. reset is asserted if the mr pin is pulled low to less than 100mv for 1s or longer while the push-button is closed or a reset is signaled. after mr is released, the reset outputs remain asserted for t por . mr input has an internal 20k pull up resistor provided. figure 3 illustrates a typical application diagram for either ic showing both reset outputs being used along with both a manual and signalled reset configuration. the v dd and v2mon thresholds are preset whereas the v3mon is capable of uv (ISL88021) or ov (isl88022) monitoring of a voltage greater than or less than 0.6v, respectively. application considerations follow good decoupling practices to prevent transients from causing unwanted reset signaling due to switching noises and short duration droops. when using the c por pin, reduce layout stray capacitance on this pin to minimize effect on t por timing. if no pcb c por pad is patterned, the t por can be 160ms. using the ISL88021_22eval1 platform the ISL88021_22eval1 board is designed to provide both immediate functional assessment and flexibility to the user. both ics are the ?hf? variant having a v dd vth of 4.64v, a v2mon vth of 3.09v and v3mon vth of 0.6v. the top ic position is the ISL88021 and is configured to monitor for undervoltage (uv) compliance of a 5v, 3.3v and a 2.5v and signaling the reset and reset outputs. the bottom position is the isl88022 variant, which is configured to measure a 3.3v overvoltage (ov) in addition to uv on both the 5v and 3.3v supplies. reset and reset is asserted for at least t por when these voltage go out of range. in both cases v3mon interfaces with the monitored supply via a simple resistor divider for comp arison to the internal 0.6v reference. a manual reset (mr ) input is provided on both ics and is invoked by pulling this input low. v3mon c por mr pb gnd rst rst to display to p reset v mon > 0.6v v2mon v dd 1.8v - 3.3v 3.3v - 5v ISL88021 isl88022 signal figure 3. typical application diagram figure 4. ISL88021_22eval1 schematic and photo ISL88021iu8hfz isl88022iu8hfz figure 5. isl88022eval1 3.3v uv and ov detection reset# responding to monitored voltage ri sing and falling ramp through the programmed uv and ov thresholds monitored voltage. c por pin is open, t por = 150ms ISL88021, isl88022
6 fn8226.1 september 18, 2006 operational timing diagrams figure 6. ISL88021_22eval1 t por comparison isl88022 t por = 150ms 3.3v rising edge 100ms/div c por = open ISL88021 t por = 390ms c por = 10pf v dd mr rst t por v th1 1v v th2 or v ref t por t por t por >t mr t rpd t rpd rst ISL88021) figure 7. ISL88021 and isl88022 timing diagram ISL88021, isl88022
7 all intersil u.s. products are manufactured, asse mbled and tested utilizing iso9000 quality systems. intersil corporation?s quality certifications ca n be viewed at www.intersil.com/design/quality intersil products are sold by description only. intersil corpor ation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of paten ts or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiari es. for information regarding intersil corporation and its products, see www.intersil.com fn8226.1 september 18, 2006 ISL88021, isl88022 mini small outline pl astic packages (msop) notes: 1. these package dimensions are wi thin allowable dimensions of jedec mo-187ba. 2. dimensioning and tolerancing per ansi y14.5m - 1994. 3. dimension ?d? does not include mold flash, protrusions or gate burrs and are measured at datum plane. mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. dimension ?e1? does not includ e interlead flash or protrusions and are measured at datum plane. interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. formed leads shall be planar wi th respect to one another within 0.10mm (0.004) at seating plane. 6. ?l? is the length of terminal for soldering to a substrate. 7. ?n? is the number of terminal positions. 8. terminal numbers are shown for reference only. 9. dimension ?b? does not include dambar protrusion. allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of ?b? dimension at maximum ma terial condition. minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. datums and to be determined at datum plane . 11. controlling dimension: millimeter. converted inch dimen- sions are for reference only. l 0.25 (0.010) l1 r1 r 4x 4x gauge plane seating plane e e1 n 12 top view index area -c- -b- 0.20 (0.008) a b c seating plane 0.20 (0.008) c 0.10 (0.004) c -a- -h- side view b e d a a1 a2 -b- end view 0.20 (0.008) c d e 1 c l c a - h - -a - - b - - h - m8.118 (jedec mo-187aa) 8 lead mini small outline plastic package symbol inches millimeters notes min max min max a 0.037 0.043 0.94 1.10 - a1 0.002 0.006 0.05 0.15 - a2 0.030 0.037 0.75 0.95 - b 0.010 0.014 0.25 0.36 9 c 0.004 0.008 0.09 0.20 - d 0.116 0.120 2.95 3.05 3 e1 0.116 0.120 2.95 3.05 4 e 0.026 bsc 0.65 bsc - e 0.187 0.199 4.75 5.05 - l 0.016 0.028 0.40 0.70 6 l1 0.037 ref 0.95 ref - n8 87 r 0.003 - 0.07 - - r1 0.003 - 0.07 - - 05 o 15 o 5 o 15 o - 0 o 6 o 0 o 6 o - rev. 2 01/03
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